Tile Calorimeter: Radiation Tests

S-LINK & Interface boards

This board is still under development. Both a preliminary and development version 3.1b have been tested.

• TID tests:
 
SRL= 0.23 Gy/10y
 
• Test 1 (1999): 1 board irradiated
• total dose applied: 99Gy
• no problems observed
• Test 2 (2001): 1 board V3.1b irradiated
• total dose applied: 12 Gy (entire board)
• total dose applied: 24 Gy (selected components)
• no problems observed
• further tests planned
RTC= 0.23 * 3.5 * 1 * 4 = 3.2 Gy for CMOS components
      = 0.23 * 3.5 * 5 * 4 = 16 Gy for BiPol components
• NIEL tests:
 
SRL= 1.5 * 10**10  n/cm**2/10y
 
• Test 1 (1999): 1 board irradiated
• total fluence applied: 5.7 * 10**12 u
• failure of a voltage regulator transistor at 5.7 * 10**12 u


RTC= 1.5 * 10**10 * 5 * 1 * 4 = 3.0 * 10**11 u
 

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Last update: 22 October 2001
Maintained by:  Richard Teuscher
(previously Philippe Grenier)