In this scheme, the signal from each calorimeter cell is sampled
continuously at 40 MHz and each sample is stored in a capacitor during
the 2 
s latency of the LVL1 trigger.
If a positive trigger decision is received,
a group of samples, centred on the corresponding bunch crossing, are read
back and digitized. At the maximum trigger rate (100 kHz),
up to five samples per event may be digitized.
The main advantage of this solution is that only interesting data are digitized, thus limiting cost and power. The challenge is to preserve the sensitive analog information for several microseconds in an environment with 40 MHz digital signals.
The electronics close to the detector should consist of the minimum necessary to send analog signals to the LVL1 trigger, and multiplexed digital data for further processing off the detector. This keeps the distance between the detector and the analog electronics as short as possible, and most of the digital electronics far from the sensitive analog part. Both features should maximize the signal-to-noise ratio.
The on-detector electronics consists mainly of shapers, analog memories, and ADCs. A dynamic range in excess of 16 bits is achieved with two shaper channels per calorimeter cell with a gain ratio of the order of 12. A memory channel is associated with each shaper channel. This consists of a set of 128 capacitors per input signal, 80 of which are occupied at any one time by data waiting for a trigger decision. The other 48 may be occupied by data accepted by the LVL1 trigger and waiting for digitization. The analog memory also acts as a derandomizing buffer before the ADCs.
A 10 MHz ADC is assigned to either 8 or 16 calorimeter cells depending on whether both high and low gain data are digitized, or only the relevant one. A link to the remote electronics is associated with each ADC, with a 200 Mb/s bandwidth (including protocol overhead).
The 64 cells associated with a given front-end board are neighbours in the same
calorimeter layer in order to ensure that the analog signals are in time.
The board size is 
mm
. Its power dissipation is 38 W. About
4000 front-end boards are needed to read out all of the channels.
The front-end crates also house calibration pulsers, control modules, and timing boards which receive and fan out the 40 MHz clock. For the trigger, the 64 analog signals from the low gain shapers on the front-end boards are summed in groups of eight and sent to tower summation boards in the same crate. The resulting analog signals are sent to the trigger system via 70-metre-long copper cables [79].
The off-detector electronics will make use of digital signal processors. They will apply calibration corrections (including non linearity corrections and, if needed, memory-cell-dependent corrections), perform optimal filtering to determine the signal time and amplitude, and format the data for the LVL2 and the DAQ systems. These same processors will be used to monitor raw data and to perform intermediate calculations during calibration runs.
The system aspects are being considered. These include the procedures to install the electronics and to debug it. Since the front-end crates will be difficult to access, monitoring will be performed remotely. Automatic tests of the various components (e.g. memory controllers, links) are also being carefully designed. Moreover, some fault-tolerance will be implemented to cope with bad components. We are also studying techniques for tuning the various delays, configuring the system, and controlling it during standard data-taking and calibration runs.
A significant effort was undertaken in several institutes to develop analog memories satisfying the speed and dynamic range requirements. Such chips now exist in the form of prototypes. A dynamic range of 13 bits has already been achieved with some of them and they will be available at a low cost in the next few years.
A 120-channel system based on the Alberta memory was used in a test beam, in association with the RD3 calorimeter. A timing precision below 0.5 ns for 100 GeV electrons, and an energy resolution identical to that of the standard RD3 readout were achieved [80]. Another analog memory system, designed at Nevis Laboratories, was recently tested at CERN on a liquid krypton accordion calorimeter prototype. This readout system has a dynamic range in excess of 13 bits for a single gain channel. Further beam tests are foreseen in 1995.
Several teams have worked independently on preliminary studies of the readout system and are now collaborating together effectively [81].